This invention relates generally to packages for housing integrated circuit devices and, more particularly, packages for housing very large integration (VLSI) circuit devices.
As is known in the art, in many applications monolithic integrated circuits are packaged in so-called "flatpacks" or "DIPS" (dual in-line packages) which are mounted on, and electrically interconnected by, a printed circuit board. The printed circuit boards are electrically interconnected by a back panel into which the printed circuit boards are plugged. The back panel is generally either of printed circuit construction or constructed to enable the desired electrical interconnections between the printed circuit boards by individual wires.
While these packaging concepts have been found useful in many applications, it is, however, characterized by relatively large parasitic capacitances resulting from relatively long interconnect wires used to interconnect the printed circuit boards. These parasitic capacitances may be sufficiently large to adversely affect their use in many low power, high density integrated circuits such as complementary metal-oxide-semiconductor (CMOS)/silicon on sapphire (SOS) circuits, short channel NMOS circuits and I.sup.2 L circuits which operate with relatively small input signal voltage swings and which, due to their relatively high output impedances, will be slowed down when forced to operate with parasitic capacitances normally associated with printed circuit board and individual wire back panel interconnects.